Start Discovering Solved Questions and Your Course Assignments
TextBooks Included
Solved Assignments
Asked Questions
Answered Questions
1 to obtain the greatest possible accuracy in a timing device you should use aa digital timer operated from a
redesign the floating-point multiplier in figure 7-7 using a common 5-bit full adder connected to a bus instead of two
write a behavioral vhdl code for a floating-point multiplier using the ieee single precision floating-point format use
this problem concerns the design of a circuit to find the square of a floating-point number f times 2e f is a
write a vhdl function that will take two integer vectors a and b and find the dot product c sigma ai bi the function
write a vhdl procedure that will add two bit-vectors that represent signed binary numbers negative numbers are
a vhdl entity has inputs a and b and outputs c and da and b are initially high whenever a goes low c will go high 5 ns
consider the following three concurrent statements where r is a resolved signal of type x01zdraw the multiple drivers
write a vhdl description of an address decoderaddress match detector one input to the address decoder is an 8-bit
write a vhdl model for one flip-flop in a 74hc374 octal d-type flip-flop with three-state outputs use the ieee-standard
in the following code all signals are 1-bit stdlogic draw a logic diagram that corresponds to the code assume that a d
design a memory-test system to test the first 256 bytes of a static ram memory the system consists of simple controller
design a memory tester that verifies the correct operation of a 6116 static ram figure 8-15the tester should store a
a clocked t flip-flop has propagation delays from the rising edge of clk to the changes in q and q as follows if q or q
write a vhdl model for an n-bit comparator using an iterative circuit in the entity use the generic parameter n to
write structural vhdl code for a module that is an n-bit serial-in serial-out rightshift register inputs to the shift
1 create a 4 times 4 array multiplier using generate statements use full adder half adder and and gate components as in
1 write a procedure that has an integer signal and a file name as parameters each line of the file contains a delay
1 what does the term isa mean do the pentium 4 and pentium 3 have the same isa2 microprocessor x has 30 instructions in
1 find a minimum set of tests that will test all single stuck-at-0 and stuck-at-1 faults in the following circuit for
instead of using dual-port flip-flops of the type shown in figure 10-8 scan testing can be accomplished using standard
based on the vhdl code of figure 10-21 design a two-cell boundary scan register the first cell should be an input cell
referring to figure 10-16 determine the sequence of tms and tdi inputs required to load the instruction register with
1 a draw a circuit diagram for an lfsr with n 5 that generates a maximum length sequenceb add logic so that 00000 is
a write vhdl for an 8-bit misr that is similar to figure 10-28b design a self-test circuit similar to figure 10-25 for