Write a VHDL description of an address decoder/address match detector. One input to the address decoder is an 8-bit address, which can have any range with a length of 8 bits; for example, bit_vector addr(8 to 15). The second input is check: x01z_vector(5 downto 0).The address decoder will output Sel = ‘1' if the upper 6 bits of the 8-bit address match the 6-bit check vector. For example, if addr = "10001010" and check = "1000XX", then Sel = ‘1'. Only the six leftmost bits of addr will be compared; the remaining bits are ignored. An ‘X' in the check vector is treated as a don't care.