Write a VHDL model for one flip-flop in a 74HC374 (octal D-type flip-flop with three-state outputs). Use the IEEE-standard nine-valued logic package. Assume that all logic values are ‘x', ‘0', ‘1' or ‘z'. Check setup, hold, and pulse width specs using assert statements. Unless the output is ‘z', the output should be ‘x' if CLK or OC is ‘x', or if an ‘x' has been stored in the flip-flop.