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What are the extreme values of vO for which Q1: and Q2: just remain in saturation?
For finite ro( /VA /= 20 V), what is the voltage gain from G to D and the input resistance at G?
Neglecting the finite base currents of Q2: and Q3: and assuming that their VBE ?0.7 V and that Q2: has five times the area of Q3: find the value of I.
If it is required to raise the gain by a factor of 2, what channel length would be required, and by what factor does the total gate area of the circuit increas
A CG amplifier operating with gm = 2 mA/V and ro =20 kOis fed with a signal source having Rs =1 kO.
If RL increases by a factor of 10, by what percentage does the current gain change?
If the maximum allowed dc voltage drop across Rs is 0.3 V, what is the maximum available output resistance of the current source?
How large can vsig be (peak-to-peak) while maintaining saturation-mode operation for Q1: and Q2.
As mentioned in the text, the C B amplifier functions as a current buffer. That is, when fed with a current signal, it passes it to the collector and supplies.
The BJT is specified to have ß =100, VBE =0.7 V, and VA = 100 V. If the collector voltage undergoes a change of 10 V while the BJT remains in the active mode.
It is required to find the incremental (i.e., small-signal) resistance of each of the diode-connected transistors shown in Figure
What is the lowest voltage at the output for which proper current-source operation is maintained?
If the deviation from unity is to be kept at 0.2% or less, what is the maximum possible number of outputs for BJTs with ß = 150?
For the base-current-compensated mirror of Figure ,show that the incremental input resistance is approximately 2VT /IREF.
If the amplifier is fed with a signal source having Rsig = 5 kO and is connected to a load of 100-kO resistance, find the overall voltage gain, vo/vsig.
Find the intrinsic gain of an NMO Stransistor fabricated in a process for which k1 n = 400 µA/V2 and V1A = 10 V µm.
An NMOS transistor fabricated in a certain process is found to have an intrinsic gain of 50 V/V when operated at an ID of 100 µA.
Consider an NMOS transistor fabricated in a 0.18-µm technology for which k1 n = 400 µA/V2 and V1 A = 5 V/µm.
Sketch the circuit for a current-source-loaded CS amplifier that uses a PMOS transistor for the amplifying device.
An NMO Stransistor operated with an overdrive voltage of 0.25 V is required to have a gm equal to that of an npn transistor operated.
Find the values of gm and A0 obtained at ID =25 µA, 250 µA, and 2.5 mA.
It was fabricated in a 0.18-µm CMOS process for which µnCox = 400 µA/V2 and V_ A = 5 V/µm.
What must W be for the NMOS transistor to operate at ID = 100 µA? Also, find the values of gm and ro.
Using a CMOS technology for which k1n = 200 µA/V2 and V1 A = 20 V/µm, design a current-source-loaded CS amplifier for operation at I = 50 µA .
The two transistors have L =0.5 µmand are to be operated at ID =100 µAand |VOV |= 0.3 V. Find the required values of VG, (W/L)1, (W/L)2, and Av .