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Find the value of R that yields a current I = 200 µA. For the BJT, VEB = 0.7 V at IE = 1 mA.
Design three Widlar current sources, each having a 100-µA reference current: one with a current transfer ratio of 0.8, one with a ratio of 0.10.
Find the voltage gain when a load resistance of 2 kO is connected to the output.
What is the effect of increasing the bias currents by a factor of 10 on Rin , Gv , and the power dissipation?
Noting that RG is connected between the input node where the voltage is vi and the output node where the voltage is Avvi , find Rin.
If the follower is fed with a source having a 100-kO resistance and is loaded with 1 kO .
Also find VS , VD1, and VD2. (b) If the current source requires a minimum voltage of 0.4 V, find the input common-mode range.
What is the maximum possible factor by which the output resistance can be raised, and at what value of Re is it achieved?
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In a MOS cascode amplifier, the cascode transistor is required to raise the output resistance by a factor of 50.
The cascode transistor can be thought of as providing a "shield" for the input transistor from the voltage variations at the output.
Which is operating at the same bias current and has the same minimum voltage requirement at the drain as in the circuit of Figure.
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For simplicity, we are assuming that the four transistors have the same gm and ro. The amplifier is fed with a signal vi.
The 0.13-µm CMOS fabrication process available has Vtp =-0.4 V, V1A =-6 V/µm, and µpCox = 100 µA/V2.
Find the overall voltage gain vo/vi and evaluate its value for the case gm1 = 2 mA/V and A0 = 30.
A cascode current source formed of two pnp transistors for which ß = 50 and VA = 5 V supplies a current of 0.2 mA.
Assume that the BJTs have ß =100 and that both the BJTs and the MOSFETs have / VA/ = 5 V.
In this problem, we will explore the difference between using a BJT as cascode device and a MOSFET as cascade device.
What will the extent of the linear region at the output become?
Find the value of the dc component that will result in the maximum possible signal swing at the output with almost-linear operation.
It is required to design the circuit to obtain a voltage gain Av = -40 V/V. Use devices of equal length L operating at I = 100 µA and / VOV/ = 0.25 V.
Assuming that Van = / VAp / and that the biasing current sources have output resistances equal to those of Q1: and Q2.
What is the peak of the largest output sine-wave signal that is possible while the NMOS transistor remains in saturation?
If Q2: and Q3: are to be operated at the same overdrive voltage as Q1: what must their W/L ratios be?