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A half-wave rectifier circuit with a 1-kO load operates from a 120-V (rms) 60-Hz household supply through a 12-to-1 step-down transformer.
At what forward voltage does a diode conduct a current equal to 10,000IS?
What happens if the transistor is replaced with another having ß=100? Give the value of VC in the latter case.
For what load resistance connected to ground is the output negative voltage limited to -1 V before Q7:begins to conduct?
CMRR Assume ß = 100, |VBE | = 0.7 V, |VA | = 60 V, Vt = 0.7 V, and kO (W/L) = 2 mA/V2.
Find A1, A2, the open-loop voltage gain, the input common-mode range, and the output voltage range.
Design so that all transistors operate at 0.2-V overdrive voltages. Specify the W/L ratio required for each MOSFET.
With A and B at a dc voltage of VDD/2, perform a dc design that will result in each of Q1:Q2:Q3:and Q4: conducting a drain current of 200 µA .
Find the input resistance of the first stage, and the current gain from the input of the first stage to the collectors of the second stage.
What should this resistor be changed to if the output resistance is to be reduced by a factor of 2?
Find the dc voltage at the output. Assume /VBE /= 0.7V, ß = 100, and neglect the Early effect.
Now, using ß=100, find the voltage gai vo/(v+ -v-), and in the process, erify the polarity of the input terminals.
Show that if all transistors are operated at an overdrive voltage VOV and have Equal Early voltages /VA .
Find the currents labeled i1 to i13 in terms of (gmvid ). Determine their values in the sequence of their numbering and assume gmro.
This problem investigates the effect of transistor mismatches on the input offset voltage of the current-mirror-loaded MOS differential amplifier.
What will the voltage gain be if the input resistance of the subsequent stage is equal to Rid of this stage?
For the current-mirror-loaded bipolar differential pair, replacing the simple current-mirror load by the base-current-compensated mirror.
What should the value of VBIAS be in order to allow for a negative output signal swing of 1.5 V?
With vI =0 V dc, find the input bias current IB assuming all transistors have equal value of ß. Compare with the case without the Q7:Q8:connection.
If I is delivered by a simple NMOS current source operated at the same VOV and having the same channel length as the other four transistors.
Recalling that for the simple mirror RSS = ro/ QS and for the Wilson mirror RSS ?gm7ro7ro5, and assuming that all transistors have the same /VA / and k1W/L.
If the common-mode output resistances of the amplifier, Ro1 and Ro2, are very large, find Acm and CMRR.
What is the expected magnitude of the deviation from unity of the current gain of the load mirror?
What is the value of the input common-mode resistance when the bias source has the lowest acceptable output resistance?
If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch.