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Inclusion of an emitter resistance Re reduces the variability of the gain Gv due to the inevitable wide variance in the value of ß.
Design a CE amplifier with a resistance Re in the emitter to meet the following specifications:
A CE amplifier utilizes a BJT with ß = 100 biased at IC = 0.5 mA and has a collector resistance RC = 12 kO and a resistance Re = 250O connected
The overall voltage gain of a CS amplifier with a resistance Rs = 0.5 kO in the source lead was measured and found to be -10 V/V
A CS amplifier using an NMOS transistor with gm = 2 mA/V is found to have an overall voltage gain of -10 V/V
For the circuit shown in Fig. draw a complete small-signal equivalent circuit utilizing an appropriate T model for the BJT (use a=0.99)
In the circuit shown in Fig the transistor has a ß of 200. What is the dc voltage at the collector?replacing the BJT with one of the hybrid-p models
Consider the augmented hybrid-p model shown in Fig. Disregarding how biasing is to be done, what is the largest possible voltage gain available for a signal
Redesign the circuit of Fig(a) by raising the resistor values by a factor n to increase the resistance seen by the input vi to 75 O
A transistor operating with nominal gm of 40 mA/V has a ß that ranges from 50 to 150. Also, the bias circuit, being less than ideal, allows a ± 20% variation
A designer wishes to create a BJT amplifier with a gm of 30 mA/V and a base input resistance of 3000O or more What collector-bias current should he choose?
The problem investigates the nonlinear distortion introduced by a MOSFET amplifier. Let the signal vgs be a sine wave with amplitude Vgs
The purpose of problem is to illustrate the application of graphical analysis to the circuit shown in Fig. Sketch iC -vCE characteristic curves for the BJT
For the NMOS amplifier in Fig.replace the transistor with its T equivalent circuit, assuming ? = 0. Derive expressions for the voltage gains vs/vi and vd /vi
In the circuit of Fig the NMOS transistor has / Vt /= 0.5 V and VA = 50 V and operates with VD = 1 V. What is the voltage gain vo/vi ?
For a 0.18-µm CMOS fabrication process: Vtn = 0.5 V, Vtp = -0.5 V, µnCox = 400 µA/V2, µpCox = 100 µA/V2, Cox = 8.6 fF/µm2, VA (n-channel devices)
Figure shows a discrete-circuit amplifier. The input signal vsig is coupled to the gate through a very large capacitor (shown as infinite).
An NMOS technology has µnCox = 250 µA/V2 and Vt = 0.5 V. For a transistor with L = 0.5 µm, find the value of W that results in gm = 2 mA/V at ID = 0.25 mA
An NMOS amplifier is to be designed to provide a 0.20-V peak output signal across a 20-k_ load that can be used as a drain resistor
Sketch the iC -vCE characteristics of an npn transistor having ß = 100 and VA =100 V. Sketch characteristic curves for iB = 20 µA, 50 µA, 80 µA
Consider an NMOS transistor having kn = 10 mA/V2. Let the transistor be biased at VOV = 0.2 V. For operation in saturation, what dc bias current ID results?
All the transistors in the circuits of Fig. are specified to have a minimum ß of 50. Find approximate values for the collector voltages and calculate forced ß
Consider a transistor biased to operate in the active mode at a dc collector current IC. Calculate the collector signal current as a fraction of IC
An npn BJT with grounded emitter is operated with VBE = 0.700 V, at which the collector current is 0.5 mA.