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In the common-gate amplifier circuit of Fig. Q2: and Q3: are matched. K1n(W/L)n = k1 p(W/L)p = 4 mA/V2, and all transistors have |Vt | = 0.8 V
For the CB amplifier, to explore the variation of the input resistance Rin with the load resistance RL. Specifically, find Rin as a multiple of re for RL/ro
The amplifier is loaded in a resistance RL = 20 kO. Find Rin and io/isig, where io is the current through the load RL
A CG amplifier operating with gm = 2 mA/V and ro =20 kOis fed with a signal source having Rs =1 kO and is loaded in a resistance RL = 20 kO. Find Rin, Rout
Find A0 for an NMO Stransistor fabricated in a CMOS process for which k1 n = 400 µA/V2 and V1 A = 6 V/µm.
What value of load resistance RL causes the input resistance of the CB amplifier to be approximately double the value of re?
Figure shows an amplifier utilizing a current mirrorQ2: Q3: Here Q1:is a common-source amplifier fed with Vi = VGS +vi , where VGS is the gate-to-source
Figure shows a current-mirror circuit prepared for small-signal analysis. Replace the BJTs with their hybrid- p models and find expressions for Rin
It is required to find the incremental (i.e., small-signal) resistance of each of the diode-connected transistors shown in Fig.
Consider the CE amplifiers of Fig. for the case of I =0.5 mA, ß =100, and VA =100 V. Find Rin , Avo, and Ro
For the base-current-compensated mirror of Fig. show that the incremental input resistance (seen by the reference current source) is approximately 2VT /IREF
Extend the current-mirror circuit of Fig.to n outputs. What is the resulting current transfer ratio from the input to each output, IO/IREF?
For the base-current-compensated mirror of Fig let the three transistors be matched and specified to have a collector current of 1 mA at VBE = 0.7 V.
Find the intrinsic gain of an NMO Stransistor fabricated in a process for which k1 n = 400 µA/V2 and V1A = 10 V µm.
Fill in the table below. For the BJT, let ß = 100 and VA = 100 V. For the MOSFET, let µnCox = 200 µA/ V2, W/L = 40, and VA = 10 V
An NMOS transistor operated with an overdrive voltage of 0.25 V is required to have a gm equal to that of an npn transistor operated at IC = 0.1 mA
Sketch the circuit for a current-source-loaded CS amplifier that uses a PMOS transistor for the amplifying device.
Consider an NMOS transistor fabricated in a 0.18-µm technology for which k1 n = 400 µA/V2 and V1 A = 5 V/µm. It is required to obtain an intrinsic gain
An NMOS transistor fabricated in a certain process is found to have an intrinsic gain of 50 V/V when operated at an ID of 100 µA. Find the intrinsic gain
A CS amplifier utilizes an NMOS transistor with L = 0.54 µm and W/L = 8. It was fabricated in a 0.18-µm CMOS process for which µnCox = 400 µA/V2
A CS amplifier utilizes an NMOS transistor with L = 0.36 µm and W/L =8. It was fabricated in a 0.18-µm CMOS process for which µnCox = 400 µA/V2 and V1A
A NMO Stransistor is fabricated in the 0.18-µmprocess whose parameters are given. The device has a channel length twice the minimum and is operated at
The MO SFETs in the current mirror of Fig. have equal channel lengths of 0.5 µm, W1 = 10 µm, W2 = 50 µm, µnCox = 500 µA/V2, and V_ A = 10 V/µm.
Assuming that Y is connected to a voltage V, a current I is forced into X, and terminal Z is connected to a voltage that keeps Q5: in the active region
Using the ideas embodied in Fig. design a multiple-mirror circuit using power supplies of± 5 Vto create source currents of 0.2 mA, 0.4 mA, and 0.8 mA