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syntax of display and strobe- display formatstring par1 par2 - strobe formatstring par1 par2 - monitor formatstring par1 par2 -
state the term in detail strobestrobe this task is very similar to display task except for a slight difference if many other statements are
what are the difference between display and strobedifference between display and strobe is that strobe displays parameters at the very end of current
state the term- display and writedisplay and write two are the same except which display always prints a newline character at the end of its
differentiate between display and strobethese commands have similar syntax and display text on screen during simulation display and strobe display
write decoder functionality in only one statement in verilog ltcodegtmodule decoder outputsdout inputsdininput 30 dinoutput 150 doutassign dout
explain the term- signals- signals are used for communication between components- signals can be seen as real physical signals- some
explain the term- variables- variables are used for local storage of data- variables are usually not available to multiple processes and
what are the various functional verification methodologiesans tlm transaction level modellinglintingrtl simulation environment involving
state the optimal route of nodeconsider the node i which has path length k1 with the directly preceding node on the path being j the distance to node
what is reentrant tasks and functionstasks and functions without optional keyword automatic are static with all declared items being statically
why disable statements are not allowed in functionsif disble statement is used in functionit invalids function and
why a function canot have delayshowever in open vera delays are allowed in function a function returns a value and hence can be used as a part of any
why a task cannot return a valueif tasks can return values then lets take a look at the below exampleaf1bf2cand f1 and f2 had delays of say 5 and 10
why a function should have at least one inputthere is no strong reason for this in verilog i think this restriction isnt removed fin systemverilog
why a function cannot call a taskas functions doesnt consume timeit can do any operation which doesnt consume time mostly tasks are written that
determine about the verilog task- tasks are capable of enabling a function as well as enabling other versions of a task- tasks also run with a zero
what is verilog function - a function is unable to enable a task however functions can enable other functions- a function would carry out its
state about the behavioral modelingbehavioral means how hardware behaves determine exact way it works we write using hdl syntax for complex projects
explain the register transfer languageregister transfer language means there must be data flow between two registers and logic is in between them for
equivalence between vhdl and cthere is concept of understanding in c there is structurebased upon requirement structure provide facility to store
what are the differences between simulation and synthesissimulation lt verify your designsynthesis lt check for your timingsimulation is used to
what are the differences between struts and units a warm up question units are static objects that exist from the start of the simulation right up
what are the special unit related fields and methods the most significant method in fact pseudo method related to units is
how can you pass a struct by reference in e the question is phrased in a tricky way because passing by reference is the default and only