What is Verilog function
- A function is unable to enable a task however functions can enable other functions.
- A function would carry out its required duty in zero simulation time.
- Within a function, no event, delay or timing control statements are permitted.
- An invocation of a function their should be at least one argument to be passed.
- Functions would only return a single value and cann't use either output or inout statements.
- Functions are synthesysable.
- Disable statements can't be used.