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  Registers, Physics tutorial

Registers:

The register is group of memory elements that stores binary word and it may alter stored word in particular fashion as is desired by application in which it is utilized. It is able to shift stored binary word a step or more towards left or right.

Buffer Register:

The simplest type of register is a buffer register that stores a binary word. It is composed of several D flip-flops, number of which depends on number of bits present in binary word. The buffer register for storing 4-bit word, X3X2X1X0 with Q3Q2Q1Q0 as its output word.

1426_Buffer register.jpg

Each flip-flop is positive edge triggered. At every clock output, Q of each flip-flop is same as input X. For this 4-bit register, we can write

Q3Q2Q1Q0 = X3X2X1X0

In chunked notation, this expression is written as

Q = X

Controlled Buffer Register:

The controlled buffer register is shown below. All flip-flops are with CLEAR that resets flip-flops when HIGH. CLEAR is inactive when LOW. Control LOAD terminal when HIGH permits input X to reach flip-flop and doesn't permit when LOW. When CLEAR is HIGH, all flip-flops reset and the stored word is Q = 0000 When CLR returns. LOW, register is ready for desired action. Control terminal LOAD determines circuit function. When LOAD is HIGH, data X is permitted to reach flip-flop.

1184_Controlled buffer register.jpg

Though when LOAD is LOW, LOAD is HIGH, that permits Q outputs to go to D inputs.

It signifies that so long as LOAD is LOW, input data X is circulated or retained at PGT of each CLK. That is, contents of register continue to remain unchanged so long as LOAD is LOW.

Shift Registers:

Shift registers move stored word towards left or right. Thus there are two kinds of shift registers - Shift-left and shift-right registers. Shifting of bits of stored word towards left or right is necessary in arithmetical operations.

Shift Left Register:

The register that shifts bits of stored word towards left, known as shift-left register, is shown below. As is clear from circuit, data input Djn sets up first flip-flop, and Q0 output of this flip-flop set up second flip-flop; Q1 sets up third and Q2 sets up fourth. Data is given to input of first flip-flop, i.e., Din and output is got simultaneously from all flip-flops, circuit is called as serial-in/parallel-out.

Working of shift-left registers can be understood by following example:

Consider that input data Din is 1, i.e., input to flip-flop-1, D0 = 1 and initial output

Q = 0000

That is, initially inputs to all other three flip-flops are 0. Now with arrival of PGT of first CLK, Q0 output is 1, and stored word becomes

Q = 0001

Now with D1 = 1 and D0 = 1, when PGT of second CLK arrives then first and second flip-flops are set, making register output to be

Q= 0011

Now D2 = 1, D1 = 1, and D0 = 1. When PGT of third CLK arrives then first, second and third flip-flops are set making register output to be

Q= 0111

Likewise when PGT of fourth CLK arrives, then output becomes

Q = 1111

Stored word is therefore 1111 and it remains unchanged so long as Din = 1. Though, if Din = 0, then with successive CLK pulses register output or content becomes

At 1st CLK Q= 1110

At 2nd CLK Q= 1100

At 3rd CLK Q= 1000

At 4th CLK Q= 0000

This word 0000 remains stored so long as Din = 0. Entire operation of shift-left register in terms of its tuning diagram is shown below.

1596_Shift Left Register.jpg

2414_Timing diagram of shift-left register.jpg

Shift Right Register:

Circuit for shift-right register is shown below. Data input, Din is given to input of fourth flip-flop as D3. Q output of each flip-flop is fed back to D input of previous flip-flop, i.e. Q3 is given to D2, Q2 is given to D1 and Q1 is given to D0. When PGT of CLK arrives, stored word shifts one step to its right.

1242_Shift Right Register.jpg

Operation of shift-right register can be explained as follows. Consider that in starting Din = 1, and Q = 0000

At arrival of PGT of the first CLK, D3 = 1, and all other D inputs are 0, thus, fourth flip-flop is set and stored word is

Q = 1000

Now D3 = 1 and D2 = 1. When PGT of the second CLK arrives, third and fourth flip-flops are set, and the stored word becomes

Q= 1100

Likewise, with arrival of PGT of third CLK, stored word becomes

Q= 1110

And with arrival of PGT of the fourth CLK, the word becomes

Q= 1111

Controlled Shift Register:

In general operation of shift register is managed by some extra arrangement so that when PGT of CLK arrives stored word must or must not change as desired by application. Such controlled shift-left register is:

2137_Controlled Shift-left register.jpg

Its operation is as follows: When control input signal SHL is 0, the inverted signal SHL‾ is 1. In this condition, Q outputs of flip-flops are circulated back to the respective D inputs. It signifies that data stored in register remains stored even at arrival of PGT of CLK. That is, stored word is stored indefinitely.

Now reverse control signal. When control input signal SHL is 1, inverted signal SHL is 0. In this condition, Din is available at D0 input, and at arrival of PGT of first CLK first flip-flop is set by D0. With successive CLKs, Q0 sets second flip-flop, Q1 sets third, and Q2 sets fourth flip-flop. At each PGT of CLK, stored word shifts a step towards left.

Loading of word to be stored in this type of register is done serially, that is the word is loaded by entering one bit per CLK. To store a 4-bit word we need four CLK pulses. For instance, X = 1001 is loaded serially as follows:

Keep SHL = 1, and make Din = 1. At first CLK

Q= 0001

Now keeping SHL = 1, make Din = 0. At second CLK

Q= 0010

At third CLK

Q= 0100

Now keeping SHL = 1, make Din = 1. At fourth CLK

Q= 1001

Data is therefore entered serially and stored word is available parallel from all Q outputs. All bits of a word can, though, be loaded simultaneously and it requires only one CLK pulse as is done in buffer register. Circuit for this type of loading can be utilized for serial and parallel loading of a word to be stored.

If LOAD and SHL are 0, output of NOR gate is 1. With this condition Q outputs are circulated back to their respective D inputs. Previously stored word continues to be stored. Register, in this state, is called as inactive register.

If LOAD is 0 and SHL is 1, register is utilized for serial loading as is done in case of register. If Load is 1 and SHL is 0, then X bits set D inputs simultaneously on first CLK itself. This is the situation of parallel loading. For the word of more bits to be stored, more flip-flops are needed. Actually you need same number of flip-flops as is number of bits in word to be stored.

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