It is required to design the circuit of Fig. 12.25 to drive a load resistance of 50Ω_ while exhibiting an output resistance, around the quiescent point, of 2.5Ω_. Operate QN and QP at IQ =1.5mA and /VOV /=0.15 V. The technology utilized is specified to have K1 n =250 μA/V2, K1 p =100 μA/V2, Vtn =-Vtp =0.5 V, and VDD =VSS =2.5 V
(a) Specify (W/L) for each of QN and QP.
(b) Specify the required value of μ.
(c) What is the expected error in the stage gain?
(d) In the quiescent state, what dc voltage must appear at the output of each of the error amplifiers?
(e) At what value of positive vO will QP be supplying all the load current? Repeat for negative vO and QN supplying all the load current.
(f) What is the linear range of vO?
