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q why fet is a voltage sensitive device explain from the drain characteristicsthe jfet consists of a thin layer of n-type material with two ohmic
q explain the ideal drain characteristics of the jfetthe jfet consists of a thin layer of n-type material with two ohmic contacts the source s and
q show the enhancement of mosfet here also the slab of p type material called the substrate is provided the substrate is connected to a source
suppose we have an array-based list a0n - 1 and we want to delete all duplicates lastposition is initially n - 1 but gets smaller as elements are
the full reaction mechanism for production of acetic acid from feed of ethylene via wacker process with acetaldehyde as an
q what are the differences between enhancement and depletion mosfetdepletion mosfethere a slab of ptype material is formed from a silicon base and
q what is schokleys equation find out a relation between vgs and idsschokleys equation is used for defining the relation between the gate source
q what is idss what are the conditions for its maximum valuethe term idss refers to saturation condition of the drain current from the above graph
q what do you mean by pinch off voltageas the voltage vds is increased from 0 to a few volts the drain current will increase as determined by
q which are the different fet amplifiersa fet can be used as a small-signal amplifier by connecting one of its lead to signal ground the other two
q what is the advantage of using jfet as an amplifieras an amplifier of small time-varying signals the jfet has a number of valuable assets first of
q give the principle of biasing a fet amplifierto correctly bias the fet the gate needs to be negative with respect to the source bias is obtained in
define the types programmable logic devicesthere are mostly three types plds these are vary in the placement of fuses in the and- or array1rom- it
define the programmable logic devices pldin the world of digital electronic systems there are three essential kinds of devices 1memory
q on a cd amplifier rs 4k micro 50 and r 35k evaluate the voltage gain av av vovi micrors micro1rs
define the meaning of registers and countingregisters group of flip-flops use for data storagecounting another extremely important application of
define frequency division - application of flip flop when the pulse waveform is applied to the clock input of a j-k flip-flop that is connected to
explain the design procedure for flip flopthe design procedure as follows1acquire the clear description of the desired flip flop x2acquire the
define the operating characteristics for master-slave s-r flip-flop1 propagation delay time - is the interval of time required subsequent to an input
define the pulse-triggered master-slave flip-flopsthe term pulse-triggered signify that data are entered into the flip-flop on the rising edge of the
q which are the three basic configurations of fet amplifiersthe three basic configurations of fet amplifiers aremiddot common sourcecs- it is most
explain the race around conditionconsider the inputs of the jk flipflop j1 and k1 and q0 when a clock pulse of width tp is applied the output will
q in a cd amplifiergiven rs 4k micro50 and rd 35k mu find the voltage gain av the voltage gain av vo vi micrors micro1 rs rd 504 103
q what the voltage gains in the fet amplifier for common source voltage gainvovi - micrord rd rdwhere micro is the amplification factorrd the
define the edge-triggered flip-flopsan edge-triggered flip-flop changes states either at the negative edge falling edge or at the positive edge