Explain the Race Around Condition?
Consider the inputs of the JK flipflop j=1 and k=1 and Q=0 when a clock pulse of width tp is applied the output will change from 0 to 1 after a time interval ?t, where ?t is the propagation delay of flipflop. Following another ?t output Q will become 0. Thus the output oscillate back and forth between 0 and 1 in duration tp of the clock pulse width. consequently at the end of the clock pulse, the value of Q is ambigious and this situation is called race around condition. The race around condition can be avoided if tp