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q for a 6-bit weighted-resistor da converter if r is the resistor connected to the msb find the other resistor values needed and calculate the
q determine the bits required for a da converter to detect 1-v change when vref 15
q counting to moduli other than 2n is a frequent requirement the most common being to count through the binary-coded decimal bcd 8421 sequence all
q sketch the timing diagram for a 4-bit ripple counter which uses t
q a for a jkffwith jk 11 the output changes on every clock pulse the change will be coincident with the clock pulse trailing edge and the flip-flop
q a shift register can be used as a binary a divide- by-2 and b multiply-by-2 counter explainq show a block diagram of a 4-bit shift-right register
q show a block diagram of a 4-bit parallel-input shift-right register and briefly explain its
q consider a series-carry synchronous counter with t flip-flops shown in figure in which the and gates carry forward the transitions of the
q consider the synchronous counter shown in figure of the texta draw its timing diagramb show the implementation of the same synchronous counter
q counting to moduli other than 2 is a frequent requirement the most common being to count through the binary-coded decimal bcd 8421 sequence all
q for a jkffwith jk 11 the output changes on every clock pulse the change will be coincident with the clock pulse trailing edge and the flip-flop is
q give a block diagram for amodulo-5 binary ripple counter using jkffs and draw its timing
q draw a block diagram of a 4-bit pipo register and briefly describe its operationq taking parallel data from a computer to be fed out over a single
q obtain a block diagram of a shift-leftright register using d flip-flopsq design a 4-bit universal shift registerq a show a block diagram of an srff
q a shift register can be used as a binary a divide by-2 and b multiply-by-2 counter explainshow a block diagram of a 4-bit shift-right register
q show a block diagram of a 4-bit parallel-input shift-right register and briey explain its
q show an arrangement for multiplexing 64-to-1 by using four 16-to-1 multiplexers and one 4-to-1
q use a 4-to-1multiplexer to simulate the followinga nand logic functionb exclusive-or logic functionc sigma m 1 2
q using two 8-to-1multiplexers and one 2-to-1multiplexer show how a 16-to-1 multiplexer can be obtained in the form of a block
q implement the following boolean functions by employing 8-to-1multiplexersa f1abc sigma mi 0 2 4 6b f2abc sigma mi 1 3
q based on the 8421 bcd code for decimal digits 0 through 9 develop a block diagram for a bcd encoder and its implementation
q illustrate bcd-to-decimal decoding with a 4-to- 16 decoder and draw the corresponding truth
q draw a block diagramfor a 2-to-4 decoder obtain the truth table and develop a logic
qa excess-3 code is a 4-bit binary code for the 10 decimal digits and is found useful in digital computer arithmetic each combination is found by
q draw the logic diagram of an sr latch using only nand gates and obtain the truth table for that