Junction field effect transistors (JFET):
Development and employment of transistors on the large scale started with Bipolar Junction Transistor and this is the most common transistor which most likely to find on printed circuit board populated with transistors. It acts as main device in, and has led to solid state electronics revolution. The main disadvantage of Bipolar Junction Transistor though is its very low input impedance that results from forward bias of Emitter-Base junction when in normal operation. Now assume junction device like Bipolar Junction Transistor that operates with input diode junction reversed biased then you have imagined the Junction Field Effect Transistor or JFET in short, which with its reverse biased input junction presents extremely high input impedance.
Many benefits are related with high input impedance. For example, having high input impedance minimizes interference with or loading of signal source when measurements are made and this is very helpful in instrumentation.
The n-channel FET is made from t bar of n-type material, with shaded areas made up of a p-type material as the Gate. Between Source and Drain, the n-type material serves a resistor. Current flow comprises of majority carriers (electrons for n-type material). As Gate junction is reverse biased and as there is no minority carrier contribution to flow through device, input impedance is very high.
Control element for JFET comes from depletion of charge carriers from n-channel. When Gate is made more negative, it depletes majority carriers from the larger depletion zone around the gate. This decreases current flow for the given value of Source-to-Drain voltage. Modulating Gate voltage modulates current flow through device.
JFET characteristic curves:
For the given value of Gate voltage, current is very almost constant over the wide range of Source-to-Drain voltages. Control element for JFET comes from depletion of charge carriers from n-channel. When Gate is made more negative, it depletes majority carriers from the larger depletion zone around gate. This decreases current flow for given value of Source-to-Drain voltage.
Transfer characteristic for JTET is helpful for visualizing gain from device and recognizing region of linearity. Gain is proportional to slope of transfer curve. Current value IDSS represents value when Gate is shorted to ground, maximum current for device. This value will be part of data supplied by manufacturer. Gate voltage at which current reaches zero is known as pinch voltage, VP.
Operation of JFET device:
Operation of Field Effect Transistor is very simple. The voltage when applied to gate, input element manages resistance of channel that is unipolar region between gate regions. In the N-channel device, channel is lightly doped N-type slab of silicon with terminals situated at each end. Source and drain terminals bear analogy to emitter and collector, respectively, of the Bipolar Junction Transistor. In the N-channel device, the heavy P-type region situated around midway on both sides of slab acts as the control electrode, the gate. Gate is also analogous to base terminal of the Bipolar Junction Transistor.
In the properly biased N-channel Junction Field Effect Transistor (JFET) the gate seems as diode junction to source-drain semiconductor slab and is reverse biased. If the voltage were applied between source and drain, N-type bar would conduct in either direction due to doping. Neither gate nor gate bias is needed for conduction. If the gate junction is formed conduction can be handled by degree of reverse bias.
The depletion region at gate junction is because of diffusion of holes from P-type gate region in N-type channel, giving charge separation about junction, with the nonconductive depletion region at junction. Depletion region extends more intensely in channel side because of heavy gate doping and light channel doping.
In figure (a) shows depletion at gate diode under zero bias voltage. In (b) with reverse biased gate diode, width of depletion region increases whereas (c) illustrates effect of increasing reverse bias that further expands depletion region. Lastly in (d) further increasing reverse bias pinches-off Source-Drain channel and conduction through semiconductor slab stops altogether.
Thickness of depletion region can be increased by applying moderate reverse bias as (b) illustrates. This increases resistance of source to drain channel by narrowing channel. Increasing reverse bias as shown in (c) increases depletion region, decreases channel width, and increases channel resistance.
Increasing reverse bias VGS at (d) will pinch-off channel current. Channel resistance will be extremely high. This VGS at which pinch-off occurs is VP, pinch-off voltage. It is naturally a few volts. The channel resistance can be handled by degree of reverse biasing on gate. The source and drain are identical, and source to drain current may flow in either direction for low level drain battery voltage (< 0.6 V). This means, drain battery can be replaced by the low voltage Alternating Current source.
For the high drain power supply voltage though, polarity should be as indicated in (a) above. This drain power supply that effect is not trivial distorts depletion region by enlarging it on drain side of gate. This is a more correct representation for common DC drain supply voltages, from a few to tens of volts. As drain voltage VDS is increased, gate depletion region expands toward drain. This raises length of narrow channel, increasing resistance modestly. Larger resistance changes are because of changing gate bias.
JFET as an amplifier:
Similar to bipolar junction transistor, JFET's can be utilized to make single stage class A amplifier circuits with JFET common source amplifier and characteristics being extremely like BJT common emitter circuit. Main benefit JFET amplifiers have over BJT amplifiers is their high input impedance that is managed by Gate biasing resistive network formed by R1 and R2 as shown.
This common source (CS) amplifier circuit is biased in class "A" mode by voltage divider network formed by resistors R1 and R2. Voltage across Source resistor RS is usually set to be about one quarter of VDD, (VDD /4 ). Required Gate voltage can then be computed using this RS value. As Gate current is zero, (IG = 0) we can set required DC quiescent voltage by proper selection of resistors R1 and R2.
Control of Drain current by the negative Gate potential makes Junction Field Effect Transistor helpful as switch and it is necessary that Gate voltage is never positive for the N-channel JFET as channel current will flow to Gate and not Drain resulting in damage to JFET. Principals of operation for the P-channel JFET are similar as for N-channel JFET, except that polarity of voltages require to be reversed.
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