A particular design of the two-stage CMOS op amp of Fig. 13.1 has Gm1 = 1 mA/V and Gm2 = 2 mA/V. The total capacitance at the output node is 1 pF. While utilizing a Miller compensation capacitor CC without a series resistance R, the amplifier is made to have a uniform -20-dB/decade gain rolloff with a unity-gain frequency ft of 100 MHz.
(a) What must the value of CC be?
(b) What do you estimate the frequencies of the poles, fP1 and fP2, and of the right-half-plane zero, fZ, to be?
(c) What is the phase margin obtained?
(d) To increase the phase margin, a resistance R is connected in series with CC. What is the value of R that results in Fz =∞, and what is the resulting phase margin?
(e) If R is increased further, until it moves the zero into the left half-plane and thus turns the phase it introduces into phase lead, what value of R is needed to obtain a phase margin of 85o?
