Problem 1: For the following circuit, the propagation delay (max delay) for the gates and Tc2q are shown. The contamination delay (min delay) is half of the propagation delay. The setup/hold time requirements are also shown. The maximum clock skew is 2ns. Assume input A does not change for a clock cycle. How fast can clock run without setup violation? Is there any hold time violation? Show your calculation.
Problem 2: Explain the following concepts
a. BGA and PGA
b. Electro-migration
c. IR drop
Problem 3: Complete the waveform, where Q1 is for a high-activate D-latch, Q2 is for a positive edge triggered D flip-flop, and Q3 is for a negative edge triggered D flip-flop. D is the input to the latch/flip-flops. Assume no delay.
Problem 4: Draw a clock tree and specify the position of its root for the following sinks. To receive any credit, the path from the root to all sinks must be the same distance. To receive full credit, the total wire length of the tree must be minimum.
Problem 5: Draw the circuit of the 6T SRAM bitcell.
Problem 6: Describe 4 methods to reduce power. If necessary, draw a circuit to demonstrate the method. State if each method reduces static or dynamic power.
Problem 7: Draw an ESD circuit.
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