You are required to design a simple CMOS circuit consisting of a two-input NOR gate. You are required to show the layout (plan view) of the circuit, after calculating the aspect ratio (W/L) of the transistors. The layout of the circuit should include the VDD and ground lines.
Marks will be awarded for the calculations, the explanation of the calculations, the layout, and the quality of the drawing of the layout. You must also hand in, with the layout, a summary of your clculations with full explnation.
Specification:
VDD = 4 V, threshold voltage of n- and p-channel MOSFETs are VTn = 0.3 V, VTp = -0.3 V respectively, oxide capacitance Co = 5x10-4 Fm-2, electron mobility 0.1 m2V-1s-1, hole mobility 0.05 m2V-1s-1, minimum feature size 0.2 μm, maximum alignment error 0.1 μm. The area of the circuit should be a minimum.
Understanding alignment and minimum feature size.
1) The minimum feature size is the smallest dimension that can defined on a chip. This will often be the channel length L.
2) The various layers have to be aligned (registered) with each other. This involves some error in placing any mask relative to the pattern already on the silicon. It is necesssary to know how large (in microns) the error can be. You must allow for this in the design.