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a 60-hz 440-v three-phase system feeds two balanced wye-connected loads in parallel one load has a per-phase impedance
repeat problem 429 for a delta-connected set of capacitors with a per-phase reactance of -j60 omega connected in
three identical impedances of 30 ang30deg omega are connected in delta to a three-phase 173-v system by conductors that
when the two-wattmeter method for measuring three-phase power is used on a certain balanced load readings of 1200 w and
two watt meters are used as shown in figure 431 to measure the power absorbed by a balanced delta-connected load
referring to problem 4215b with a phase voltage as the reference phasor and with a positive phase-sequence supply
an op amp has a slew rate of 07 vmicros find the maximum amplitude of an undistorted output sine wave that the op amp
an inverting amplifier is designed with three inputs v1 v2 and v3 as shown in figure p548 determine the output voltage
analyze the 2-bit r-2r ladder-network da converter and corresponding to binary 01 10 and 11 obtain the equivalent
for a 6-bit weighted-resistor da converter if r is the resistor connected to the msb find the other resistor values
counters are used to realize various dividers in the schematic representation of the digital clock shown in figure
figure p6230 shows the mod-8 counter which counts from 010 to 710 before resetting explain the operation of the counter
consider a series-carry synchronous counter with t flip-flops shown in figure p6229 in which the and gates carry
for the 4-bit da converter of figure 629 calculatea the maximum analog output voltageb the minimum analog output
a design a 6-bit r-2r ladder da converterb for vref 10 v find the maximum output voltagec determine the output voltage
consider the 4-bit r-2r ladder da converter with vref -10 v determine the analog output voltage when the binary input
an 8-bit ad converter is driven by a 1-mhz clock estimate the maximum conversion time ifa it is a counter-controlled ad
suppose a rom holds a total of 8192 bitsa how many bits long would the individual addresses have to beb if the bits are
show the schematic arrangement for a one dimensional addressing and b two-dimensional addressing see problem 6245 if a
repeat problem 6246 if a 64-kbit rom is to provide a 16-bit output wordproblem 6246show the schematic arrangement for a
a show a block diagram of an srff connected to store 1 bitb using 4 srffs obtain the block diagram for an siso shift
taking parallel data from a computer to be fed out over a single transmission line needs a piso device develop a block
sketch the timing diagram for a 4-bit ripple counter which uses t flip-flops see problem 6225problem 6225a for a jkff
lab exercisesyou have been hired to create the logic for a program that produces a profit report for items sold by the
counting to moduli other than 2n is a frequent requirement the most common being to count through the binary-coded