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  Pulses

Introduction to Pulse Details:

Horizontal Sync & Blanking Pulse Detail

For an entire Horizontal line the line period is 64u sec. within that Retrace time period is 12u sec: trace line period is 52u sec:

VERTICALSYNCAND BLANKING PULSE DETAIL

The one field's time period is 20m sec. In this, vertical trace is 18.72m sec and 1.28m sec is for retrace.

SERRATED SYNC PULSES

To prevent the interruption to the field sync because of line sync, the vertical sync pulses are separated into 5 half-lines containing time period of 4.7u sec. This is termed as Serrated Sync pulses. To carry out this within Interlaced scanning method, in odd fields to start half-line 312.5  and in even field the line.625 (half-lines), these types of pulses are ready to five half-lines (27.3u sec).

EQUALIZING PULSES

The vertical oscillator generates potential level known as trigger level. Trigger level intersects the two filter outputs profiles at dissimilar points. That points out that in the case of second field the oscillator will acquire triggered a fraction of a second very soon as compared to the first field. Note: this dissimilarity in potential levels for the two fields carries on throughout the period of discharge of the capacitor. One time the vertical sync pulses are over and the horizontal-pulses take over. However the actual time variation is fairly short it does prove enough to upset the wanted interlacing sequence.

Be careful of this drawback that takes place on account of the half-line discrepancy five narrow pulses are added on either side of the vertical sync pulses. These are termed as pre-equalizing and post-equalizing pulses.

PRE-EQUALIZING PULSES

Pre-equalizing pulses is of 2.3p second duration result in the discharge of the capacitor to necessarily zero voltage in both the fields, in spite of the half-line discrepancy before the voltage build up begins with the arrival of vertical sync pulses.

POST-EQUALIZING PULSES

Post-Equalizing pulses are essential for a fast discharge of the capacitor to make sure triggering of the vertical oscillator at appropriate time. If the decay of voltage beyond the capacitor is slow like would occur in the nonexistence of post-equalizing pulses, the oscillator might trigger at the trailing edge that may be far away from the leading edge and this could direct to an error in triggering.

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