What is Synchronous reset?
Synchronous reset:
Synchronous reset logic will synthesize to smaller flip-flops, mainly when the reset is gated along with the logic generating the d input. Although in such a case, the combinational logic gate count develops, therefore the overall gate count savings may not be that important. The clock acts as a filter for small reset glitches; though, when these glitches happen near the active clock edge, the Flip-flop could go metastable. Into some designs, the reset should be produced by a set of internal conditions. A synchronous reset is proposed for these types of designs since this will filter the logic equation glitches among clocks.