Read Architecture: Look Through
Main memory that located is conflicting the system interface. The least concerning feature of this cache unit is that it remain between the processorand main memory. It is essential to notice that cache sees the processors bus cycles before let it to pass on to the system bus. Look Through the Read Cycle Example When the processor initiatea memory access, the cache checks if that address is a cache hit.
- HIT: The cache responds to the request of the processor without beginning an access to main memory.
- MISS: The cache passes the bus cycle onto the system bus. Main memory then responds to the request of the process. Cache snarfs the data so that in the next time the processor requests this data, it will be calledcache hit. This architecture let the processor to run out of cache when any another bus master is accessing main memory, since the processor is inaccessiblefrom the rest of the system. However, thecache architecture is complicated because it might be able to control accesses to the rest of the system. The increasing thecomplexity increases the cost. Another bad side is that memory accesses on cache misses are slower because main memory is not accessed till after the cache is checked. This is not an fact if the cache has a high hit rate and there are other bus masters.