Read Architecture : Look Aside Cache
In "look aside" cache architecture the main memory is located conflictingthe system interface. Both the cache main memory sees a bus cycle at the same time. Hence it name is "looks aside."
Look Aside Cache Example:
When the processor begin a read cycle, the cache checks to see if that address is a cache hit.
- HIT: If the cache has the memory location, then the cache will respond to the read cycle and then terminate the bus cycle.
- MISS: If the cache does not contain the memory location, then themain memory will give respond to the processor and then stop the bus cycle. The cache will snarf the data, so in next time the processor requests this data it will be a cache hit. Look aside caches are less complicated, which makes them less costly. This architecture also provides better response to a cache miss since the DRAM and the cache both see the bus cycle at the same time. The drawback is the processor can't access cache while another bus master is accessing main memory.