Question 1) Compute RC time constant for the 1cm long doped polysilicon interconnection runner on the 1μm thick SiO2. Polysilicon has the thickness of 5000Ao and a resistivity ρ of 1000μΩ-cm. Find the number of gates which can be included on the logic-gate array chip which is to be assembled in a 100 I/O package. Describe the thermal design considerations of packaged silicon devices. Describe the molecular beam epitaxial process for the silicon device fabrication with neat and suitable sketches of the growth system.