The speed of a transistor is directly proportional to the width of its polysilicon gate; thus, a narrower gate results in a faster transistor and a wider gate in a slower transistor. Knowing that the manufacturing process has a certain variation for the gate width (say, ± 0 .1 μ m), how would a designer modify the gate size of a critical circuit in order to minimize its variation in speed? Are there any negative effects of this change?