Design sense-amplifier gates using each of the following circuit families to compute an 8-input XOR function in a single gate: SSDL, ECDL, LCDL, DCSL1, DCSL2, DCSL3. Each true or complementary input can drive no more than 24 Q of transistor width. Each output must drive a 32/16 Q inverter. Simulate each circuit to determine the setup time and clock-to-out delays.