Design the basic cell of a universal shift register to thefollowing specifications. The internal storage elements will bepositive edge-triggered D flip-flops. Besides the clock, theshifter stage has two external control inputs, S0 andS1, and three external data inputs, SR, SL, and DI. SRis input data being shifted into the cell from the right, SL isdata being shifted from the left, and DI is a parallel-load data.The current value of the flip-flop will be replaced according tothe following settings of the control signals: S0 =S1 = 0: replace D with DI; S0 = 0,S1 = 1: replace D with SL; S0 = 1,S1 = 0: replace D with SR; S0 = S1= 1: hold the current state. Draw a schematic for this basic shifter cell.