In this question you will consider the effects of parasitic interconnect capacitance on the switching speeds of CMOS and n-MOS logic. To model the effects of this parasitic capapacitance, assume that the interconnect lines are Ld,, wide and of average length rnLmin, where m is a number much greater than 1, also assume that the thickness of the oxide under the lines is such that their capacitance per unit area is aC&, where a is a fraction much less than 1.
(a) Derive an expression analogous to Eq. (16.45) for the switching transients in CMOS when the interconnect loading is accounted for through the model just desscribed. CMOS inverters made using this process.
(b) Do the same as in part a for an n-MOS invertor.
(c) Assuming the multiplicative factors m and a are the same for CMOS and nMOS, for what values of m and a does CMOS become faster than n-MOS. Assume Wn = Lmin.
(d) Calculate the switching speed for CMOS and n-MOS inverters fabricated by the process described in Problem 16.12 when the average length of interconnect that each inverter drives is 60 pm (Le., m = 40) and when the thickness of the oxide under the interconnect lines is 600 nm (i.e., a = 0.05).