In a pipelined processor, each TLB entry consists of 32 bits of data and 36 bits of tag. The page size used by the processor is 16 kB and the block size is 64 B. Each of the L1 caches consists of 32 kB of data and are 2-way set-associative; the L2 cache is 512 kB large and is 4-way set-associative; and, the L3 cache has 8 MB and is 8-way set-associative. All read/write caches employ write back and write allocate strategies. The clock frequency is 3 GHz. Accessing a block from L2 consumes 10 ns, from L3 takes 20 ns, and from main memory 30 ns.
a.Calculate the numbers of tag, index and offset bits in each cache.
b.Calculate the execution time of a program that involves completion of 3 millioninstructions,40% of which are load or store. The instruction cache has a hit rate of 99%,data cache 85%, L2 cache 70%,and L3 cache 50%.