Question: Design an address decoder for the following 68000 system:
a. 256 Kbytes of ROM (using 128K x 8-bit chips)
b. 4 Mbytes of RAM1 (using 512K x 4-bit chips)
c. 4 Mbytes of RAM2 (using 1M x 1-bit chips)
2. A memory board has 2 Mbytes of RAM composed of 256K X 8 RAM chips located at address $A0 0000 onward. The board also has a block of 256 Kbytes of ROM composed of 128K x 8 chips located at address $F8 0000. Design an address decoder for this board.