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  Dynamic Characteristics of MOS Transistor Inverter

MOS Transistor Inverter: Dynamic Characteristics:

MOS Inverter with Capacitive Loading:

A schematic figure of the simple MOS transistor inverter with capacitive load is as shown below in figure below. Operation is governed by identical considerations as in case of bipolar transistor inverter. Whenever the transistor is conducting, it actively contributes to driving the load; however whenever it is off then the output conditions become heavily load dependent.

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Figure: Circuit of Capacitively Loaded Simple MOS Inverter

Transistor Turn-Off and Inverter Rise-Time:

When the switching of transistor is taken as ideal, then whenever the transistor is turned off, the capacitor just charges up exponentially via RD. This is similar process for any C-R charging circuit and hence similar expressions will apply for 10% and 90% points of the output voltage as in case of the bipolar transistor inverter. As a result, an almost similar expression is obtained for 10% to 90% rise time as shown:

tR = 2.2CL RD

When CL = 10pF and RD =100kΩ, then tR = 2.2µs.

This is much greater than in case of the bipolar transistor inverter since of much higher value of resistor RD that is employed since of the lower levels of current in the MOS transistors.

Transistor Turn-On and Inverter Fall-Time:

In this situation, the transistor conducts and plays an active role in discharging the capacitance through drawing the charge from it. The waveform of output voltage is as shown in figure below. At first the output voltage will be at supply voltage, VDD, with capacitance completely charged. When an input voltage of Vi = VDD is applied to the gate of transistor, then this signifies that initially the transistor executes with VGS = VDD and with VDS = VDD and hence VDS > VGS – VT and thus the transistor executes in the saturation region as shown in the waveforms. Once the output voltage drops beneath the supply voltage by an amount equivalent to the threshold voltage, then VDS < VGS – VT and the transistor executes in non-saturation region. Eventually, the capacitor will be discharged to the value of output logic LO voltage, VOL, determined formerly. As can be seen from waveform, usually the 90% point will be reached whereas operating in the saturation region however the 10% point will be reached as operating in the non-saturation region. This complexes the solution of equations for fall-time. A further complication is a square term in the expression for drain current whenever operating in the non-saturation region that makes it harder to obtain a solution. This is cumbersome and the trouble can be simplified when approached in a different way.

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Figure: A Waveform of the Output Voltage from the Capacitively Loaded MOS Inverter

Things can be simplified when the transistor is treated just as a current source containing an average value of current iD AVE discharging the capacitor as shown in figure below. The average current can be taken as the average of initial and final values of current throughout the discharging operation.

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Figure: Equivalent Circuit with MOS Transistor as a Current Source

The initial value of current can be as the value for operation in saturation with Vi = VDD as:

iD(t = 0) = Kn (VDD - VT)2

The final value of current can be taken as current flowing via the load resistor RD whenever the capacitor has been discharged to minimum voltage of VOL , which with VOL > 0 is as:

iD(t → ∞) = (VDD - VOL)/RD ≈ VDD/RD

This then provides the average current as:

ID AVE = [Kn(VDD - VT)2 + (VDD/RD)]/2

From the circuit above, by using Kirchhoff’s Current Law this can be seen that:

iD AVE = iRD - iCL

iD AVE = [(VDD - Vo)/RD] – CL (dVo/dt)

Dividing across through CL and rearranging provides:

dVo/dt + (1/CLRD) Vo = (VDD/CLRD) – (iD AVE/CL)

By taking the Laplace transform with VO(t=0)=VDD and re-organizing provides:

[s + (1/CLRD)]Vo(s) = VDD + (VDD/sCLRD) – (iD AVE/sCL)

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As prior to, we want to identify the 90% and 10% points on waveform. Thus at t = t90 with VO = 0.9VDD then,

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And hence: tf = 20ns

This is once again a little higher than for bipolar transistor inverter since of higher value of load resistance.

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