Introduction to Flip-Flop:
1. SR Flip-Flop
State diagram:
S
R
Q
Comment
0
1
Initial
Set
Reset
-
Not allowed
2. CSR Flip-Flop
C
Since clock is absent
no action
No change
*
3. D-Type Flip-Flop:
Logic
Input
Output
D
4. T-Type Flip-Flop
T
Qn+1
Qn
5. JK - FLIP FLOP
State diagram
Logic input
J
K
Since
clock is absent no action
Toggling
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