Deriving probability of error for binary phase shift keying


Question 1)a) Construct a feedback shift register of length m=5 and feedback connections [6,5,2,1] and initial state is 100000.Obtain the feedback and output code of the Maximal Length sequence. Verify whether it satisfies balance property

b) Derive properties of Cyclic codes.

Question 2) Perform Viterbi Algorithm to the received sequence [1111111101] for a ½ convolution encoder with constraint length 3 and whose paths are [1,1,1] and [1,0,1]. Decode the errors and give the corresponding message. Draw the Convolution encoder, Trellis code and State Diagram (Initial states are a=00, b=10, c=01 and d=11).

Question 3)a) Derive probability of error for Binary Phase shift Keying modulation and relate it with Q function. Plot the constellation diagram. Describe the transmitter and Receiver section of BPSK.

b) Compute the transmitted power spectral density of a coherent frequency hop system. The system employs BPSK modulation with a data rate of 1 MBPS. The hop rate is 100 * 103 hops/sec. The frequency spacing equals the data rate and four frequencies are employed.

Question 4)a) Describe the performance of coherent Direct sequence spread spectrum in pulse noise jamming.

b) Plot a constellation diagram for QPSK modulation and estimate the minimum Euclidean distance.

Question 5) Describe in detailed about Broad band ISDN Architecture.

b) Describe the effects on different cases of congestion in Frame relays.

Question 6)a) Describe the operation of DLCI in a Frame Relay Network.

b) Describe in detailed about SONET system hierarchy.

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Electrical Engineering: Deriving probability of error for binary phase shift keying
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