The counter is equivalent of binary odometer. It counts number of CLK pulses that arrive at CLK input. Essentially, there are two kinds of counters, asynchronous (ripple) and synchronous.
Asynchronous (Ripple) Counter:
4-bit binary counter circuit is made by using JK flip-flops. All JK inputs are kept at 1. CLK signal is given to CLK input of first flip-flop. Q0 output is given to CLK input of second flip-flop Q1 output is given to CLK input of the third, and so on. CLR input is activated when it is made 0. All CLR inputs have been attached together so that all flip-flops could be reset simultaneously. Such a counter where each flip-flop output acts as CLK input for next flip-flop is called as asynchronous counter. This name is given as all the flip-flops don't change state in exact synchronism with CLK pulses. Only first flip-flop responds to CLK pulse, whereas all others wait for previous flip-flops to change state. Thus, there is delay between responses of consecutive flip-flops. This kind of counter is also called as ripple counter.
Operation of the ripple counter:
Clock pulses are applied to CLK input of first flip-flop. Since flip-flops are driven by NGT of CLK, with J = K = 1, first flip-flop toggles when CLK pulse goes from 1 to 0. Q1 output of second flip-flop toggles when Q0 output of first flip-flop goes from 1 to 0, and so on. With CLR = 0, all flip-flops are reset to
After resetting keep CLR = 1. Now counter is prepared to count. Q0 toggles for each NGT. Thus, when NGT of first CLK arrives, then Q output is
At second CLK, Q0 toggles from 1 to 0 which serves as NGT for CLK input of second flip-flop, Q1 output of which toggles to 1. Thus,
Q = 0010
At third CLK, Q0 toggles from 0 to 1, and there is no change in Q1. Thus,
Q = 0011
At fourth CLK, Q0 toggles from 1 to 0, resulting in toggling of Q1 from 1 to 0. Q1 going from 1 to 0 serves as NGT for CLK input of third flip-flop, Q2 output of which toggles from 0 to 1. Thus,
Q output of counter at each CLK is:
Next CLK resets alt flip-flops and Q outputs on successive CLK would be
16 0000 (recycles)
While analyzing Q outputs, we find that whenever flip-flop resets to 0, output of next flip-flop is 1. That is, resetting of the flip-flop sends carry to next higher flip-flop. Thus, counter serves like a binary odometer. Q0 output of first flip-flop serves as a LSB and that of last flip-flop as MSB. This would now be clear as to why asynchronous counter is known as ripple counter. It is due to carry in output moves like a ripple on water.
Mod of Counter:
Counter described above has 16 distinct states or outputs (0000 to 1111). It is stated that Mod number of this counter is 16. The Mod number of the counter is equal to number of states which counter goes through in each complete-cycle before it recycles back to starting state.
Mod number can be increased by increasing number of flip-flops. If n is number of flip flops utilized in counter, then
Mod Number = 2n
It is clear that frequency of Q0 output is half frequency of the CLK. Q0 output serves as CLK to second flip-flop, and frequency of its Q1 output is half the frequency of Q0 or one-fourth the frequency of CLK.
First flip-flop divides by 2
Second flip-flop divides by 4
Third flip-flop divides by 8
Fourth flip-flop divides by 16
mth flip-flop divides by 2n
There is a lot of time delay in ripple counter as carry has to pass through n flip-flops. Thus, ripple counters are very slow. If Tpd is time delay for one flip-flop, then for n flip-flops time delay is n Tpd. Thus, there is a requirement for synchronous counter in which all flip-flops respond on every CLK pulse simultaneously. Circuit for a synchronous counter is given in Synchronous counter
CLK inputs of all flip-flops are joined with each other so that CLK signal reaches them simultaneously. Likewise, CLR inputs of all flip-flops are joined with each other so that they can be reset concurrently by making CLR = 0. All J and K inputs have not been joined to each other as is ease in ripple counter. JK inputs of first flip-flop are always kept at 1. Flip-flops toggle at arrival of PGT of clock pulse at their CLK inputs provided their JK inputs are at 1. Operation of this counter stated as follows:
When reset in beginning, Q output is
At arrival of PGT of first CLK, Q0 toggles from 0 to 1 bringing JK inputs of second flip-flop also to 1. Now this flip-flop is also ready to toggle. Though, by now PGT of CLK pulse has disappeared. It has to wait for PGT of second CLK. As is clear from circuit, JK inputs of third and fourth Flip-flops continue to be at 0, therefore they are in no change condition. Therefore, at arrival of first CLK,
Now at PGT of second CLK 0 Q toggles from 1 to 0 and 1 Q toggles from 0 to 1. Though, JK inputs of third flip-flop continue to be at 0 as inputs to AND gate (output of which is joined to the JK inputs) are Q1 = 1 and Q0 = 0. Thus, it is in no change condition and therefore Q2 continues to be at 0. Likewise, JK inputs of the fourth flip-flop are at 0 as Q2 = 0 and thus Q3 continues to be at 0. Therefore, at the arrival of PGT of second CLK,
At arrival of PGT of third CLK, JK inputs of second, third and fourth flip-flops are at 0; thus they are in no change condition. Only first flip-flop is ready to toggle from 0 to 1. Therefore at third CLK,
Now as Q1 and Q0 are at 1, thus JK inputs of third flip-flop are at 1. Though, JK inputs of fourth flip-flop are still at 0. Therefore first three flip-flops are ready to toggle at arrival of PGT of fourth CLK. Therefore Q0 and Q1 toggle from 1 to 0, and Q2 toggles from 0 to 1. Thus, at fourth CLK,
Successive, Q outputs are 0101, 0110, and 0111. At arrival of eighth CLK, JK inputs of all flip-flops are at 1. Q outputs of all flip-flops toggle, and we have
The Q output at each CLK is summarized in Table.
At arrival of PGT of next CLK, counter resets to Q = 0000. The counter of any length can be built by adding more number of flip-flops. Benefit of synchronous counter is that it needs only one propagation delay time in getting Q output. Mod of this counter is also 16 (=24).
Controlled Synchronous Counter:
Circuit of controlled synchronous counter is shown below. COUNT is control input. When COUNT is at 0, JK inputs of all flip-flops are at 0 keeping flip-flops in no change condition. When COUNT is at 1, the circuit is the synchronous counter.
Ring counter doesn't count binary number. The Q output of this counter has only single 1 bit and all other bits are 0. At each CLK bit 1 shifts a step to its left. Digital circuit of ring counter is shown below. It is composed of D flip-flops. Note that CLR inputs of second, third and fourth flip-flops are joined with PRESET input of first flip-flop. It signifies that when CLR is brought to 0, it presets Q0 to 1, and resets Q1, Q2 and Q3 outputs to 0.
Working of ring counter can be explained as:
When CLR is made active, i.e., when it is made 0, first flip-flop is set and all others are reset. Thus, Q output is
Now Q3 = 0 is fed back to D0 input of first flip-flop. Thus, at arrival of PGT of first CLK, Q0 is 0 and Q1 is 1, while Q2 and Q3 continue to be 0. Therefore, at first CLK,
At time PGT of second CLK arrives, D0, D1 and D3 are at 0, and D2 is at 1. Thus, Q output is,
Likewise at arrival of PGT of third CLK, Q output becomes,
PGT of the fourth CLK begins cycle again, and
Therefore we find that bit 1 shifts step to its left and it rotates back to initial position, and so on. It is due to this effect that it is called as ring counter. Instead of ring of four bits, if you want bigger ring then add more flip-flops.
Mod 10 (Decade) Counter:
Mod number of Mod 10 counter is 10, i.e., it counts from 0 to 9 and then resets to 0. This is asynchronous counter and its digital circuit is given below.
Circuit counts from 0000 to 1001 and then resets to 0000. As described in ripple counter, Q outputs of counter at arrival of NGTs of first nine CLK pulses are summarized
Circuit skips states from 10 to 15, i.e., from 1010 to 1111. Circuit is made to skip the states by combination of NAND and AND gates present in circuit. Idea is that when Q = 1010 is expected at tenth CLK, flip-flops must be cleared to be reset to 0000 that is done by bringing CLR input to 0. This is attained by connecting Q1 and Q3 to inputs of NAND gate that gives output 0 when inputs are 1 (which is case when Q = 1010 is expected at tenth CLK). Output 0 of NAND gate makes AND gate output to be 0. This makes CLR active and flip-flops reset to
Q = 0000
When CLR is a made inactive, i.e., when CLR = 1, counter becomes ready to count once again. As it takes 10 CLK pulses to reset counter, frequency of Q3 output is one-tenth of that of CLK. It is thus called a divide-by-10 circuit. It is utilized in BCD applications and frequency counters.
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