Theory of Construction and Mechanism of Operation

Construction and Mechanism of Operation:

Physical Structure:

The physical structure of an n-type MOS Transistor is as shown in figure below. It can be seen to be composed of two heavily doped n-type regions, termed to as source and drain, diffused to a lightly doped p-type substrate, also termed as bulk or body. These are spaced a distance L μm separately and extend across geometry for a width W μm. Among these two regions, on the surface of substrate, is deposited an insulating layer of Silicon Dioxide SiO2, of thickness tox, generally between 10 and 50 nm. Ultimately, this oxide layer is covered with a metal layer (or in more current years polysilicon) termed to as gate. The metal connections are then made to gate, source and drain as the terminals. There is generally a connection to the body as well and this can be made for individual transistors whenever required in today’s technologies.

The three central layers basically form a parallel plate capacitor and it is that layered structure that gives the device its name, the Metal Oxide Semiconductor or the MOS Transistor. This capacitor consists of a capacitance per unit area of Cox = εox/tox. This is the action of creating an electric field across the capacitor to control conducting channel in the silicon that forms the basis of operation of the device and provides it its full name Metal Oxide Semiconductor Field Effect Transistor or MOSFET.

The n-type, drain and source regions are reasonably highly doped at a concentration of between 1016 to 1018 cm-3 whereas the p-type substrate is lightly doped at a concentration of order of 1013 cm-3. The device shown in figure below is termed to as an n-type MOSFET since, as will be seen, the conducting channel formed is n-type. The p-type MOSFET can be fabricated by diffusing p-type drain and source regions into an n-type substrate.

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Figure: Physical Structure of the MOSFET

Device Operation:

Voltage sources are generally joined to the n-type MOS transistor as shown in figure below, which presents a vertical section view through the centre of the device.  The voltage joined between gate and source is known as VGS while that connected between drain and source is known as VDS. A voltage may also be connected between the source and the body as shown, but very often the source and body terminals are connected together.

i) All Terminals Grounded, VGS = 0 and VDS = 0
   
Initially consider the condition where all terminals of the MOSFET, comprising the body or substrate are joined to ground. Beneath this condition, p-n junctions will be made between the source-substrate and drain-substrate regions that appear basically back-to-back. As a result, depletion regions are made around the source and drain as shown in figure below and there is a tremendously high resistance to current flow among such two terminals. The depletion regions have positive ions on n-type side and negative ions on p-type side of the junctions. Since the substrate is much lightly doped, the depletion regions will expand further into the substrate than to the source or drain regions.

The energy band diagram for metal, insulator and semiconductor sandwich is as shown in figure below. Whenever such three materials are brought altogether, their individual energy bands should realign and hence the Fermi level is constant all through three materials. This realignment occurs in a different way to the junction formed in bipolar transistor, as carriers can’t pass via the insulating dielectric. Rather an electric field is made up across the insulating oxide layer and at its boundary with the substrate. This field is totally dependent on the difference in work function of the metal, qΦM and that of semiconductor, qΦS. The work function is the energy needed to eliminate an electron from the Fermi level in a particular material and is quoted for the material in isolation. The electric field gives mount to the gradient in energy profile of the oxide from the metal towards semiconductor as shown. This as well gives mount to a bending of energy levels in the surface region of semiconductor just beneath the oxide. Notice that this has the consequence of bringing the Fermi level at doped semiconductor surface nearer to the Fermi level of intrinsic silicon. The Fermi potential, ΦF, occurs from the difference between the Fermi level of p-type substrate in MOS structure and that of intrinsic silicon that is dependent on the doping concentration NA and is as follows:

ΦF = (EF - Ei)/q = (kT/q) ln (ni/NA)

This is the negative quantity for p-type silicon. At the surface of semiconductor this potential is termed as the surface potential, ΦS, that can be seen to be less than the Fermi potential since of the bending of energy bands in this region.

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Figure: Conditions in MOSFET with all the terminals Grounded

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Figure: Energy Band Diagram MOSFET with each and every terminal Grounded

(ii) Small Applied Gate Bias, VGS > 0 and VDS = 0

Let next; consider a small positive bias voltage applied to gate, whereas the drain-to-source voltage is kept at zero. It will cause positive charge to be accumulated on the gate electrode and will raise the electric field across the insulator. This has the consequence of repelling the mobile holes back to the substrate material leaving at the back negatively ionized dopant atoms at the surface of semiconductor to balance the charge accumulated on the gate electrode. In actuality, thermally available electrons occupy the vacant energy levels in the dopant acceptor atoms beneath the influence of voltage applied to the gate that holds them in position. It now causes the depletion of region to extend all along the surface of semiconductor between the drain and source as shown in figure below.

The energy band diagram beneath this condition is as shown in figure below. This can be seen that the Fermi levels in metal and semiconductor now separate under the persuade of external potential applied to the gate, VGS, by an amount equivalent to qVGS. This can also be seen that raised bending of energy bands at the surface of semiconductor brings the Fermi level of the substrate closer to the intrinsic Fermi level. With further rise in gate voltage, the width of depletion region at semiconductor surface rises. At the same time, energy bands continue to bend till the Fermi level in the semiconductor becomes equivalent to the intrinsic level if ΦS = 0. At this point, the depletion region beneath the gate is almost devoid of free charge carriers.

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Figure: Case in MOSFET, Small Gate Bias VGS > 0 and VDS = 0

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Figure: Energy Band diagram for Small Gate Bias VGS >0, VDS = 0

(iii) Increased Gate Bias, Weak Inversion, VGS < VT, VDS = 0

Figure below shows the case as the gate voltage is raised further and figure below exhibits how the energy bands in semiconductor bend further and hence the Fermi level at the surface now becomes bigger than the intrinsic Fermi level. Beneath this condition, more electrons are attracted to the region of semiconductor beneath the oxide than are needed to ionise the p-type dopant atoms. Such electrons are readily supplied by heavily doped n-type drain and source regions to form a thin conducting layer directly beneath the oxide termed as the channel. This procedure is termed as inversion whereby the originally p-type semiconductor now becomes basically n-type in the channel region, beneath the influence of electric field resultant from the applied gate voltage. When a voltage is applied between the source and drain, at this point a current will flow among them. Initially, a channel of much low conductivity is formed and the resultant current is much small and this state is termed to as weak inversion.

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Figure: Conditions at Weak Inversion, when 0 <VGS <VT and VDS = 0

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Figure: Energy Band Diagram at Weak Inversion, 0<VGS< VT and VDS=0

(iv) Increased Gate Bias, Strong Inversion, VGS > VT

When the gate voltage is raised even further, n-type conducting channel at the surface of semiconductor becomes much heavily impregnated with free electrons and thus becomes more conducting as shown in figure below. This permits a much greater current to flow among drain and source if a voltage is applied among such two terminals. This state is termed as strong inversion. In practice, there is a slow change from the weak inversion state to the strong inversion state, though channel conductivity does mount notably once strong inversion is reached. Further raise in the gate voltage above this value just leads to raised conductivity of the induced channel and higher levels of current flow between source and drain for a given potential difference among them.

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Figure: Conditions at Onset of Strong Inversion, VGS =VT, VDS = 0

Threshold Voltage VT:

For the aims of device modelling and circuit analysis it is highly enviable to encompass a definite point marking the transition from weak to strong inversion. The point utilized is termed as the threshold voltage VT, of the MOSFET.

The threshold voltage is stated, for an n-channel device, as gate-source voltage that causes the n-type conducting channel to have similar concentration of electrons as p-type substrate consists of holes.

The energy band diagram of figure below shows that at threshold voltage, the energy bands encompass bended to bring the Fermi level above the intrinsic Fermi level at the surface of semiconductor by similar amount as it is beneath it in the p-type region away from surface. At this point ΦS = -ΦF. An expression for threshold voltage will be derived afterwards. At this point as well the depletion region reaches its utmost depth. Any further raise in the gate-source voltage above the threshold value provides negligible raise in the depth of depletion region.

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Figure: Energy Bands at Onset of Strong Inversion, VGS = VT, VDS=0

CMOS Structures:

The MOS transistor shown in first figure is an n-channel device, therefore termed as the induced conducting channel is n-type and charge carriers are electrons. Note that the current flow is due entirely to electrons and therefore this device can be thought of as a unipolar transistor. The p-channel MOS transistor can be fabricated by diffusing heavily doped p-type drain and source regions into a lightly doped n-type substrate. In this device, the induced channel will be p-type and current will entirely flow due to holes.

CMOS or Complementary Metal Oxide Semiconductor technology joins both n-type and p-type devices on similar chip. Figure below shows the geometry of a CMOS pair of transistors where the major substrate is p-type and this is employed for n-channel transistors. A lightly doped n-type region termed as an ‘n-well’ is then diffused adequately, deeply into the p-type substrate therefore as to act as a secondary substrate for p-channel devices. This is termed as n-well CMOS technology and its complement p-well technology as well exists.

The other well-established technology to emerge is ‘twin-tub’ CMOS technology, which is as shown in figure below, that uses both n-wells and p-wells and diffused into a main substrate which may be of either n-type or p-type material.

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Figure: A CMOS Transistor Pair employing n-Well Technology

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Figure: A CMOS Transistor Pair using Twin-Tub Technology

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