CMOS logic families:
The primary fundamental distinction within the CMOS logic families is between the static logics and the dynamic logics.
It is a logic in which the functioning of circuit is not synchronized by the global signal, namely the clock of circuit. The output is exclusively function of the input of circuit, and this is asynchronous with respect to them. The timing of circuit is stated entirely by its internal delay.
The principal static families are:
Conventional static logic:
This is the logic normally termed when speaking of the static logic. The static circuit consists of same number of NMOS and PMOS transistors; however the n and p branches are correspondingly one dual of the other.
This is an evolution of the yet exceeded NMOS logic. This is obtained by replacing the whole PMOS branch in a static logic with a solitary PMOS transistor with its gate joined to ground. Therefore this PMOS is forever conducting and leads the output node to high state. If the NMOS branch conducts as well, then the output discharges, if the ratio among the PMOS and NMOS transistor is well designed.
The pass-logic is comparatively new logic, and, for most of digital designs, implementation in pass-transistor logic (PTL) has been exhibited to be superior in terms of timing, area and power characteristics to the static CMOS.
It is a logic in which the output is synchronized by the global signal that is the clock. The output is then; function both of the inputs of circuit and of the clock signal; and the timing of circuit is stated both by its internal delay and by the timing of clock.
Domino logic and N-P Domino logic:
Throughout the pre-charge phase, the clock is at its low state, and hence the pre-charged node prior to the static inverter is high, and the output is low. Throughout the evaluation phase, the clock is high, and hence the inputs of n-block (which can execute any logical function) can discharge the pre-charged node and lead the output to its high state.
Cascode voltages switch logic (CVSL):
The CVSL is a part of large family of differential logics. It requires both the inputs and inputs negated, and two complementary n-block which perform the logic function
The usual CMOS gate is fundamentally a three-state gate, as when the clock is at low state, the output is floating at high impedance state.
True Single Phase Clock logic (TSPC):
This logic is a n-p logic, as of each gate exists the n-version and p-version.
Both the static and dynamic logics understand numerous logic families.The CMOS (or Complementary Metal Oxide Semiconductor) logic family employs both N-type and P-type MOSFETs (improvement MOSFETs, to be more accurate to realize various logic functions. The two kinds of MOSFET are designed to encompass matching characteristics. That is, they show similar characteristics in switch-OFF and switch-ON conditions. The major benefit of CMOS logic family over bipolar logic families explained so far lies in its very low power dissipation, that is near-zero in static conditions. However, CMOS devices draw power only whenever they are switching. This permits integration of a much larger number of CMOS gates on a chip than would have been probable with bipolar or NMOS.
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