Designing a write buffer and explain how to design it.
Question- You are designing a write buffer between a write through L1 cache and a write back L2 cache.
The L2 cache write data bus is 16 B wide and can perform a write to an independent cache address every 4 processor cycles
Program-What would the effect of possible L1 misses be on the number of required write buffer entries for systems with blocking and non-blocking caches?