Assume a 64 bit processor with instruction set similar to MIPS in that the only memory instructions are LOAD and STORE to/from register, and all other instructions are R-format (suitably extended for 64 bits). You have 64 registers and a 5 stage pipeline. L1 cache returns in 1 cycle, L2 cache takes 4 cycles for an L1 miss.
Cache is write-through handled in hardware without CPU action, memory has a 20 cycle initial delay and after that supplies one word per cycle, and an L2 miss has a 40 cycle cost and loads 20 words into cache.
You are asked to design a 12 core chip where each core is as described, and will run at 2GHz. What memory bandwidth is required to support all 12 cores? Look up current memory bus speeds - are they sufficient to our requirements?
State all assumptions. (Note that: 1. You will need to make some assumption about the typical instruction mix. 2. You may need to make other assumptions. 3. Not all the given information is relevant to this problem.)