Prepare a Verilog testbench for Universal Shift Register module
Program: Write a Verilog testbench for Universal Shift Register module. The testbench will instantiate the USR, redefining its parameter to N = 4, generate a clock signal, and apply a stimulus sequence to the USR inputs.
Use the testbench clock to control when the stimulus signals change.
I prepare this but it's not working. Can you please help me to prepare a new code.