1. For a direct-mapped cache design with 32-bit address, the followingbits of the address are used to access the cache.
TAG
INDEX
OFFSET
i.
31-10
9-4
3-0
ii.
31-12
11-5
4-0
a. What is the cache line size in bytes? And how many lines does the cache have?
Starting from power on, the following byte-addressed cache references are recorded. Address
0
4
16
132
232
160
1024
30
140
3100
180
2180
b. What is the hit ratio? How many blocks are replaced?
c.List the final state of the cache, with each valid entry represented as a record of .