What are problems of clock skew?
This is typically because of two causes. The primary is a material flaw that causes a signal to travel faster or slower than imagined. The second is distance: when the signal has to travel the whole length of a circuit, this will likely (depending onto the circuit's size) arrive at diverse parts of the circuit at different times. The clock skew can cause harm into two ways. Assume that a logic path travels by combinational logic through a source flip-flop to a destination flip-flop. When the destination flip-flop receives the clock tick later than the source flip-flop, and when the logic path delay is short sufficient, in that case the data signal might arrive at the destination flip-flop before the clock tick, vanishing there the previous data which should have been clocked by. This is termed as a hold violation since the previous data is not held long adequate at the destination flip-flop to be properly clocked by. When the destination flip-flop receives the clock tick previous than the source flip-flop, then the data signal has which much less time to reach the destination flip-flop before the next clock tick. When this fails to do so, a setup violation happens, so-called since the new data was not set up and stable before the subsequently clock tick arrived. A hold violation is graver than a setup violation since this cannot be fixed by increasing the clock period.