Question: 1. Why is it much harder to design a data cache than an instruction cache?
2. To what extent do the 68020 instruction cache and the 68030 instruction and data caches impinge on
(a) the hardware systems designer and
(b) the operating systems programmer?
3. If my fairy god-person were to offer to grant me the ability to design systems that lacked one class of faults (e.g., no timing errors, no logic errors, no faulty chip errors, and no bus contention errors), I would without hesitation settle for freedom from errors due to cache systems. Why?