A certain CMOS process has a minimum gate length and width of 1.5 pm and runs off a 5-V supply with l-V threshold voltages. The electron mobility in the channel is 300 cm2N · s; the oxide thickness is 5 nm.
(a) Assuming Kn = Kp and taking n to be 4, calculate the switching time for CMOS inverters made using this process.
(b) Calculate the power delay product PDP for this same technology.
(c) Consider now scaling this process by a factor of 5/3. Initially assume the supply and threshold voltages remain unchanged.
Then scale them by a factor of 5/3 also. Calculate the switching time and PDP for these two situations. Assume that the mobility remains the same as the oxide thickness is reduced, but be aware that in practice it may actually decrease somewhat.