Design a moderate-gain (Av is close to 10) common-emitter amplifier with stabilized bias including an emitter resistor, but without a bypass capacitor. Use a 2N3904 npn transistor with a +15V dc power supply. The minimum useful bandwidth of the amplifier should range from 10Hz to 100KHZ, and this can be determined by the frequency of vin.The maximum peak value of vin is 0.5V. The specified coupling capacitors(non-polarized) are anticipated to comply with the low-cut-off frequency specification. The load for this amplifier will be another small-signal transistor circuit with an input resistance of 10K, and a resistor will simulate it.
Using only standard resistor values, select Re, and design r1,r2,and Rc for bias stability, a Q point near the center of the load line, and the desired gain. Plot the dc load line on the family of curves to help determin the appropriate values of r1, r2, and Rc?