A 6T SRAM cell is fabricated in a 0.13-μm CMOS process for which VDD = 1.2 V, Vt = 0.4 V, and μnCox = 500 μA/V2. The inverters utilize (W/L)n =1. Each of the bit lines has a 2-pF capacitance to ground. The sense amplifier requires a minimum of 0.2-V input for reliable and fast operation.
(a) Find the upper bound on W/L for each of the access transistors so that VQ and VQ do not change by more than Vt volts during the read operation.
(b) Find the delay timet encountered in the read operation if the cell design utilizes minimum-size access transistors.
(c) Find the delay timet if the design utilizes the maximum allowable size for the access transistors.