E15: Fundamentals of Digital Systems - Fall 2015 - HOMEWORK 11
1. Consider the 4 x 4 RAM module depicted below:
The module is disabled when enable is 0, and the semantics of the read/write input are 1 for read, or 0 for write. The data outputs are all 0 unless both enable and read/write are 1, in which case they reflect the value of the currently addressed word.
a. Draw a logic diagram which implements an 8 x 4 RAM module by combining two 4 x 4 RAMs along with any additional gates or components necessary. Hint: for this problem, you will need a third address line, A2.
b. Draw a logic diagram which implements a 4 x 8 RAM module by combining two 4 x 4 RAMs along with any additional gates or components necessary.
In both problems above, please clearly tie together any shared inputs or outputs of the two ROM's.
2. The following three examples of 12-bit Hamming code words are listed in the following order (with first parity bit on the left and last data bit on the right):
|
Bit position
|
1
|
2
|
3
|
4
|
5
|
6
|
7
|
8
|
9
|
10
|
11
|
12
|
|
Designation
|
P1
|
P2
|
D1
|
P4
|
D2
|
D2
|
D4
|
P8
|
D5
|
D6
|
D7
|
D8
|
For each code below, provide the 8-bit decoded (and corrected, if necessary) data bits.
a. 001110101010
b. 111010000110
c. 000010010111