The exclusive-OR circuit of Fig. 3.32(a) has gates with a delay of 4 ns for an inverter, a 8 ns delay for an AND gate. and a 10 ns delay for an OR gate. The input of the circuit goes from xy= 00 to xy = 01.
(a) Determine the signals at the output of each gate from r = 0 to r = SO ns.
(b) Write a Verilog gate-level description of the circuit, including the delays.
(c) Write a stimulus module. and simulate the circuit to verify the answer in part (a).
