Question: Synchronizer Design: You must design an interface for a data channel where the clock frequency nominally matches your system clock but may be off by as much as l,000 ppm (IQ-3). The channel sends data in blocks of 104 symbols separated by fields of at least 20 null symbols. Describe how to design a synchronizer for this channel. Sketch your design, describe its storage requirements, and explain how it operates when the clock mismatch is at either extreme (fast or slow).