Sketch the pg network for a modified 16-bit sklansky adder, Electrical Engineering

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Sketch the pg network for a modified 16-bit sklansky adder

1. Design a fast 8-bit adder. The inputs may drive no more than 30 Q of transistor width each and the output must drive a 20/10 Q inverter. Simulate the adder and determine its delay.

2. Sketch the PG network for a modified 16-bit Sklansky adder with fanout of [8, 1, 1, 1] rather than [8, 4, 2, 1]. Use buffers to prevent the less-significant bits from loading the critical path.

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Electrical Engineering: Sketch the pg network for a modified 16-bit sklansky adder

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Electrical Engineering: Sketch the pg network for a modified 16-bit sklansky adder

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